vllm.v1.simple_kv_offload.cuda_mem_ops
¶
Low-level CUDA/HIP memory helpers: pinning and batch DMA transfers.
Functions:
-
copy_blocks–Copy blocks via cuMemcpyBatchAsync / hipMemcpyBatchAsync.
-
pin_tensor–Pin a CPU tensor via cudaHostRegister.
_load_hip_runtime()
¶
Load libamdhip64, tolerating installs without the devel symlink.
The unversioned libamdhip64.so only ships with the ROCm devel package;
runtime-only and wheel-packaged ROCm installs provide just the versioned
soname. dlopen returns the already-mapped library when asked for a
soname the process has loaded — torch loads HIP at import — so the
versioned names resolve even when they are not on the loader search path.
Source code in vllm/v1/simple_kv_offload/cuda_mem_ops.py
_num_attrs_for_hip_version(version)
¶
numAttrs for hipMemcpyBatchAsync given a HIP runtime version int.
ROCm 7.2.1-7.2.3 reject numAttrs > 0 (ROCm/clr @ rocm-7.2.1
hipamd/src/hip_memory.cpp:2819-2822); 7.13+ accept it. version 0
(unknown) yields the conservative 0.
Source code in vllm/v1/simple_kv_offload/cuda_mem_ops.py
_resolve_batch_memcpy()
¶
Resolve the batch-memcpy entry point and its numAttrs (one-time).
CUDA uses cuMemcpyBatchAsync; ROCm uses hipMemcpyBatchAsync.
Raises RuntimeError if the symbol is unavailable (old CUDA driver,
ROCm < 7.1, unusual install).
Source code in vllm/v1/simple_kv_offload/cuda_mem_ops.py
_resolve_max_batch_descriptors()
¶
Max copy descriptors to pass to one batch-memcpy call (0 = unlimited).
ROCm's hipMemcpyBatchAsync faults above 8192 descriptors per call, so
on ROCm we cap and chunk larger transfers. CUDA's cuMemcpyBatchAsync
handles arbitrary counts and is left uncapped. Set
VLLM_KV_OFFLOAD_MAX_BATCH_DESCRIPTORS (>0) to override on any platform.
Source code in vllm/v1/simple_kv_offload/cuda_mem_ops.py
_rocm_num_attrs(lib)
¶
numAttrs for hipMemcpyBatchAsync on the running HIP runtime.
Source code in vllm/v1/simple_kv_offload/cuda_mem_ops.py
copy_blocks(src_block_ids, dst_block_ids, params)
¶
Copy blocks via cuMemcpyBatchAsync / hipMemcpyBatchAsync.
Source code in vllm/v1/simple_kv_offload/cuda_mem_ops.py
pin_tensor(tensor)
¶
Pin a CPU tensor via cudaHostRegister.
This bypasses PyTorch's CUDACachingHostAllocator which rounds
every pin_memory=True allocation up to the next power of 2
(e.g. 100 GB becomes 128 GB).